USA-based Siemens Digital Industries Software has developed a fully automated solution to help integrated circuit (IC) design teams identify and address electrostatic discharge (ESD) issues driven by the growing complexity of today’s next-generation IC designs, irrespective of the targeted process technology. Combining the power of Siemens’ Calibre® PERC™ software with the proven SPICE accuracy of its AI-powered Solido™ Simulation Suite, it provides a fast and accurate method for checking compliance against foundry rules spanning all phases of IC design.
Siemens Digital Industries has introduced a fast, accurate ESD verification solution for use in IC design.
Supporting full-chip level verification, the solution helps engineering teams better manage design and manufacturing challenges in established or emerging process nodes. Its context-aware checks can help to improve the accuracy of results and reduce turnaround time for physical, circuit, electrical and reliability IC design verification.
The context-aware checking allows design teams to verify ESD paths quickly, in time to secure waivers from foundry rules that can lead to smaller die sizes and optimised designs – in turn helping design teams quickly make data-driven decisions, reportedly 8x faster than current methods.
Foundry ESD rules are designed to prevent ESD failures while accommodating the diverse design styles submitted by fabless companies globally. However, these rules may be overly conservative for specific design styles and mission profiles. By rapidly identifying and simulating ESD paths that might fail foundry rules with detailed transistor-level breakdown models, the new Siemens software identifies at-risk paths with SPICE-level precision, allowing for fast, targeted and automated fixes.
“Siemens’ new ESD simulation solution can help deliver accurate reliability assessment for complex IC designs,” said Silicon Labs’ Michael Khazhinsky, Principal ESD Engineer of Central R&D. “The push-button solution integrates dynamic simulation results from Solido into a full-chip Calibre PERC result that can be used to determine quickly if designs are electrically robust. In the event of circuit errors, the Siemens solution identifies nets and devices that need to be improved.”
Automated context-aware IC design verification can now become a best practice, helping the timely delivery of reliable IC chips to market. Featuring functionalities such as automated voltage propagation, voltage-aware design rule checking, and the integration of physical and electrical information within a logic-driven layout framework, it helps design teams working to tight schedules.
"Siemens is empowering design teams to address the complexities of modern IC design reliability verification more quickly," said Michael Buehler-Garcia, Vice President of Calibre Product Management at Siemens Digital Industries Software. “This integration combines the strengths of our dynamic simulation from Solido and sign-off level ESD verification in Calibre PERC. The integrated solution speeds up the verification process and ensures the reliability of IC designs, helping our customers achieve their goals more efficiently. This is the first in a series of solutions planned, leveraging different elements of our software portfolio to speed up overall design cycle time."
For more information visit: https://eda.sw.siemens.com/en-US/